The present invention is related to systems, circuits and methods for amplifying and/or latching a differential input.
High speed, accurate sense and latch devices form the basis of a sampling system to recover the clock and data in high speed serial data links. In addition, it may be desirable for such sense and latch devices to offer power efficiency and to be less sensitive to process variations and work with a large range of input signal amplitudes and reference voltages to which an input may be compared.
Turning to FIG. 1, a conventional latch based sense amplifier circuit 100 is shown. Sense amplifier circuit 100 includes five N-type transistors 110, 112, 120, 122, 140; and four P-type transistors 130, 132, 134, 136. In particular, a differential pair includes N-type transistor 110 and N-type transistor 112 with the gate of N-type transistor 110 connected to a positive input 102, and the gate of N-type transistor 112 connected to a negative input 104. The sources of N-type transistors 110, 112 are connected to the drain of N-type transistor 140. The gate of N-type transistor 140 is connected to a clock signal 160, and the source thereof is connected to ground. The drain of N-type transistor 110 is connected to the source of N-type transistor 120, and the drain of N-type transistor 112 is connected to the source of N-type transistor 122. The gate of N-type transistor 120 is connected to the gate of P-type transistor 134, and the gate of N-type transistor 122 is connected to the gate of P-type transistor 136. The drain N-type transistor 120 is connected to the drains of P-type transistors 130, 134, and the drain N-type transistor 122 is connected to the drains of P-type transistors 132, 136. The gates of P-type transistors 130, 132 are connected to clock signal 160, and the sources of P-type transistors 130, 132, 134, 136 are connected to a power source (VDD). A negative output 150 is connected to the drains of P-type transistors 130, 134, to the gate of P-type transistor 136 and to the gate of N-type transistor 122; and a positive output 152 is connected to the drains of P-type transistors 132, 136 and to the gate of P-type transistor 134 and to the gate of N-type transistor 120.
In operation, a differential voltage is applied across positive input 102 and negative input 104. When clock signal 160 is asserted high, the voltages Di+ and Di− are discharged at a differential rate controlled by the difference between positive input 102 and negative input 104. The discharge of voltages Di+ and Di− causes transistors 120 and 122 to turn on, and develop a differential voltage across positive output 152 and negative output 150. Such circuits have become very popular as they achieve fast decisions due to the positive feedback in the latch portion of the circuit, and their differential input enables a low offset. Further, this type of circuit offers a high input impedance and an almost rail to rail voltage swing for positive output 152 and negative output 150. However, the stack of transistors used in the circuit requires substantial headroom (i.e., at least four VDS) which makes the circuit difficult to implement in low-voltage deep-submicron CMOS technologies.
Turning to FIG. 2, a double tail sense amplifier circuit 200 is presented. Double tail sense amplifier circuit 200 resolves some of the aforementioned problems with headroom. An input stage of double tail sense amplifier circuit 200 includes two N-type transistors 230, 232, two P-type transistors 220, 222, and an N-type transistor 245. The source of P-type transistor 220 and the source of P-type transistor 222 are electrically coupled to a power source (VDD). The gate of P-type transistor 220 and the gate of P-type transistor 222 are electrically coupled to a clock input 210. The drain of P-type transistor 220 is electrically coupled to the drain of N-type transistor 230, and the drain of P-type transistor 222 is electrically coupled to the drain of N-type transistor 232. The gate of N-type transistor 230 is electrically coupled to a positive input 234 (IN+) and the gate of N-type transistor 232 is electrically coupled to a negative input 236 (N−). The source of N-type transistor 230 and the source of N-type transistor 232 are electrically coupled to the drain of N-type transistor 245. The gate of N-type transistor 245 is electrically coupled to clock input 210, and the source of N-type transistor 245 is electrically coupled to ground. The input stage provides a positive output 224 (Di+) from the drain of N-type transistor 230, and a negative output 226 (Di−) from the drain of N-type transistor 232.
A latch stage of double tail sense amplifier circuit 200 includes two differential pairs each including two N-type transistors. A first differential pair includes two N-type transistors 260, 262, and the second differential pair includes two N-type transistors 270, 272. The latch stage further includes two P-type transistors 250, 252, and a P-type transistor 240. The source of P-type transistor 240 is electrically coupled to the power source (VDD), the gate of P-type transistor 240 to an inverted clock 215. The drain of P-type transistor 240 is electrically coupled to the source of P-type transistor 250 and to the source of P-type transistor 252.
The gate of N-type transistor 260 is electrically coupled to negative output 226, and the gate of N-type transistor 272 is electrically coupled to positive output 224. The source of N-type transistor 260, the source of N-type transistor 262, the source of N-type transistor 270 and the source of N-type transistor 272 are electrically coupled to ground. The drain of N-type transistor 260 and the drain of N-type transistor 262 are electrically coupled to the drain of P-type transistor 250. The drain of N-type transistor 270 and the drain of N-type transistor 272 are electrically coupled to the drain of P-type transistor 252. The gate of N-type transistor 262 is electrically coupled to the gate of P-type transistor 250, and the gate of N-type transistor 270 is electrically coupled to the gate of P-type transistor 252. The latch stage provides a positive output 280 (Out+) from the drain of P-type transistor 250, and a negative output 282 (Out−) from the drain of P-type transistor 252.
In operation, a first input is applied to positive input 234 and a second input is applied to negative input 236. When clock input 210 is asserted high (i.e., inverted clock input 215 is asserted low), the voltages at positive output 224 and negative output 236 are discharged at a differential rate controlled by the difference between positive input 234 and negative input 236. The discharge of the voltages at positive output 224 and negative output 226 causes transistors 220 and 222 to turn on, and develop a differential voltage across positive output 224 and negative output 226. The differential voltage between positive output 224 and negative output 226 is regenerated or amplified by the positive feedback of the latch stage. The positive feedback causes a small differential voltage between positive output 224 and negative output 226 to be reflected as an amplified and stored differential voltage between positive output 280 and negative output 282. While the aforementioned circuit provides a reasonable latch based sense amplifier, it requires a differential clock—one clock and an inverted version of that clock. The clock must be distributed in such a way that it transitions at substantially the same time or you get a glitch or the circuit may not work. For example, where the clock skew between clock input 210 and inverted clock input 215 is too great, there is a potential that N-type transistor 245 and P-type transistor 240 would turn on and off out of sync such that the information on positive output 224 and negative output 226 is lost and not latched. Such clock distribution is possible for relatively low frequency operation, but at higher frequency operations such clock distribution becomes costly in terms of semiconductor area and power dissipation, and in any event can be time consuming to implement and test. This problem is exacerbated in situations where a number of the aforementioned circuits are implemented and are required to operate at specified time increments thus multiplying the care that must be taken in distributing the clock and inverted clock signals.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems, circuits and methods for amplifying and/or latching a differential input.